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dual bootstrapped 12 v mosfet driver with output disable adp3418 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features all-in-one s y nchronous buck driver bootstrapped high-side dri v e 1 pwm signal generates both drives anticross-conduction protecti on circuitry output disable control turns o ff both mosfets to float the o u tput per inte l? vrm 10 and amd o p tero n specificatio ns applic ati o ns multiphase des k top cpu supp lies single-supply s y nchronous buck converters general description the ad p3418 is a d u al , hig h v o l t a g e m o s f et dr i v er o p timize d fo r dr iving t w o n-chan nel mo s f e t s, t h e two s w itc h es i n a non i s o l a te d, s y n c h r onou s , bu ck p o we r c o n v e r te r . e a ch of t h e d r i v e r s i s ca p a b l e o f d r i v in g a 3000 pf load wi th a 30 n s tra n si ti o n t i me. one o f t h e dr i v ers ca n b e b o o t st r a pp e d , a nd is desig n e d to ha ndle the hig h v o l t a g e s l ew ra te as s o c i a t e d wi t h f l o a tin g hig h - side ga t e dr i v ers. th e ad p3418 in c l udes o v erla p p i n g dr i v e p r o t ecti o n t o p r ev e n t sh oo t- th r o ugh curr e n t i n th e e x t e rn al mos f e t s. the od p i n sh u t s o f f b o t h t h e hig h -side a nd t h e l o w - s i de mo sf e t s to pre v e n t r a pi d output c a p a c i tor di s c h a rge d u r i n g sys t e m sh u t down s. the ad p3418 is s p ecif ie d o v er th e comm er cial t e m p era t ur e ra n g e o f 0c t o 85c, a nd is a v aila b l e in an 8-le ad so i c pa c k a g e . func tio n a l block di agram 03229-b - 001 r sq q cmp 1v vcc 6 delay delay 5 7 cmp 2 3 od 4 adp3418 c vcc bst vcc drvh sw drvl pgnd in 6 1 c bst1 r bst1 8 r g c bst2 d1 to inductor q1 q2 12v fi g u r e 1 .
adp3418 rev. b | page 2 of 16 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 timing characteristics ..................................................................... 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 low-side driver ............................................................................ 9 high-side driver .......................................................................... 9 overlap protection circuit ...........................................................9 application information ................................................................ 10 supply capacitor selection ....................................................... 10 bootstrap circuit ........................................................................ 10 mosfet selection ..................................................................... 10 pc board layout considerations ................................................. 12 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 8/04data sheet changed from rev. a to rev. b updated figure 1; deleted figure 2.....................................................1 updated specifications table ...............................................................3 updated pin description......................................................................5 updated theory of operation .............................................................9 updated applications section............................................................10 change to ordering guide.................................................................14 4/04data sheet changed from rev. 0 to rev. a updated format...................................................................... universal change to general description ...........................................................1 change to figure 13 ..............................................................................8 change to ordering guide.................................................................12 3/03revision 0: initial version
adp3418 rev. b | page 3 of 16 specifications 1 vcc = 12 v, bst = 4 v to 26 v, t a = 0c to 85c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit supply supply voltage range v cc 4.15 13.2 v supply current i sys bst = 12 v, in = 0 v 3 6 ma od input input voltage high 2.6 v input voltage low 0.8 v input current C1 +1 a propagation delay time t pdh od see figure 3 25 40 ns t pdl od see figure 3 20 40 ns pwm input input voltage high 3.0 v input voltage low 0.8 v input current C1 +1 a high-side driver output resistance, sourcing current v bst ? v sw = 12 v 1.8 3.0 ? output resistance, sinking current v bst ? v sw = 12 v 1.0 2.5 ? transition times t rdrvh see figure 4, v bst ? v sw = 12 v, c load = 3 nf 35 45 ns t fdrvh see figure 4, v bst ? v sw = 12 v, c load = 3 nf 20 30 ns propagation delay 2 t pdhdrvh see figure 4, v bst ? v sw = 12 v 40 65 ns t pdldrvh v bst ? v sw = 12 v 20 35 ns low-side driver output resistance, sourcing current 1.8 3.0 ? output resistance, sinking current 1.0 2.5 ? transition times t rdrvl see figure 4, c load = 3 nf 25 35 ns t fdrvl see figure 4, c load = 3 nf 21 30 ns propagation delay 2 t pdhdrvl see figure 4 30 60 ns t pdldrvl see figure 4 10 20 ns timeout delay sw = 5 v 240 ns sw = pgnd 90 120 ns 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 for propagation delays, t pdh refers to the specified signal going high, and t pdl refers to it going low.
adp3418 r e v. b | pa ge 4 o f 1 6 absolute maximum ratings table 2. p a r a m e t e r r a t i n g vcc C0.3 v to +15 v bst dc C0.3 v to vcc + 15 v <200 ns C0.3 v to 36 v bst to sw C0.3 v to +15 v s w dc C5 v to +15 v < 200 ns C10 v to +25 v drvh sw C 0.3 v to bst + 0.3 v drvl (< 200 ns) C2 v to vcc + 0. 3 v all other inputs and outputs C0.3 v to vcc + 0.3 v operating ambient temperature range 0c to 85c operating junct i on t e mperature range 0c to 150c storage temperature range C65c to +150c junction-to-air t h ermal resista n ce ( ja ) 2-layer board 123c/w 4-layer board 90c/w lead temperature (soldering, 10 s) 300c infrared (15 s) 260c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . a b s o l u te max i m u m ra t i n g s a p ply in d i vid u a l ly o n ly , n o t i n com b in a t ion. u n less o t h e r w is e sp e c i f ie d , a l l v o l t a g es are re f e re nc e d t o p g n d . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adp3418 r e v. b | pa ge 5 o f 1 6 pin conf iguration and fu nction descriptions 03229-b - 002 drvh 8 sw 7 pgnd 6 drvl 5 bst 1 in 2 3 v cc 4 ad3418 top view (not to scale) od f i gure 2. pin config ur ation ta ble 3. pi n f u nct i on d e s c ri pt i o ns pin o. nemonic description 1 bst upper mosfet floating bo otstrap supply. a ca pacitor co nnect ed between the bst and sw pins holds this boot str a pped v o ltage f o r t h e hig h - s id e mosfet as it i s swi tched. the capacitor should be bet w e e n 100 nf and 1 f . 2 in logic level inpu t. this pin has pr imary control of the drive outputs. 3 od output disable. when low, this pin disab l es n o r m al oper a tion, f o rcing drvh and drvl low. 4 vcc input supply. t h is pin sh ould be bypa ssed to pg nd with ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output dri ve for the lower (synchr o nous rectifier) mosfet. 6 pgnd power ground. should be closely co nnected to t h e source of the lower mosfet. 7 sw this pin is connected to the buc k switc hing n o de, close to the u pper mosfets source. it is the floating return for the upper mosfet drive signal. 8 drvh buck drive. output dri ve for the upper (buck) mosfet.
adp3418 r e v. b | pa ge 6 o f 1 6 timing characteristics drvh o r drvl 90% 10% od t pdlo d t pdho d 03229-b - 003 f i gure 3. o u tput d i sable t i m i ng d i agr a m in drvl drvh-sw sw t pdldrvl t fdrvl t pdhdrvh t rdrvh t pdldrvh t rdrvl t fdrvh t pdhdrvl v th 1v v th 03229-b - 004 f i g u re 4. ti ming d i ag r a m. ti m i ng is re f e r e n c ed t o t h e 9 0 % and 1 0 % point s , unles s ot her w is e n o ted .
adp3418 r e v. b | pa ge 7 o f 1 6 typical perf orm ance cha r acte ristics 2 3 1 dr v l dr v h in 03229-b - 005 f i gure 5. dr vh r i se and dr vl f a ll t i mes 03229-b - 006 2 3 1 dr v l dr v h in f i gure 6. dr vh f a ll and dr vl r i se times 03229-b - 007 junction temperature (c) 125 0 2 5 5 0 7 5 100 r i se tim e ( n s) 40 35 30 25 20 v cc = 12v c load = 3nf drvh drvl f i gure 7. dr vh and dr vl r i se times vs. t e mp e r atu r e 03229-b - 008 junction temperature ( c ) 125 0 2 5 5 0 7 5 100 fall time (ns) 26 24 22 20 18 16 drvl drvh v cc = 12v c load = 3nf f i gure 8 . dr vh a n d dr vl f a l l t i m e s vs . t e m p er a t u r e 03229-b - 009 load capacitance (nf) 5 1234 r i se tim e ( n s) 60 50 40 30 20 10 t a =2 5 c v cc = 12v drvh drvl f i g u re 9. dr v h and dr v l r i s e tim e s v s . l oad capa cit a nc e 03229-b - 010 load capacitance (nf) 5 1234 fall time (ns) 35 30 25 20 15 10 t a =2 5 c v cc = 12v drvl drvh f i g u re 10. dr v h an d dr v l f a ll ti mes v s . l oad cap a c i t a nce
adp3418 r e v. b | pa ge 8 o f 1 6 03229-b - 011 in frequency (khz) 1200 0 200 400 600 800 1000 s u p p l y curre nt (ma) 60 40 20 0 t a =2 5 c v cc = 12v c load = 3nf f i gure 11. sup p l y current v s . f r equ e nc y 03229-b - 012 junction temperature ( c ) 125 0 2 5 5 0 7 5 100 s u p p l y curre nt (ma) 16 15 14 13 12 v cc = 12v c load = 3nf f in = 250khz f i gure 12. sup p l y current v s . t e mper at ur e 03229-b - 013 v cc voltage (v) 5 0 1234 drv l outp ut v o ltage (v ) 5 4 3 2 1 0 t a = 25 c c load = 3nf f i g u re 13. dr v l o u t p ut v o lt ag e v s . sup p ly v o lt ag e
adp3418 rev. b | page 9 of 16 theory of operation the adp3418 is a dual mosfet driver optimized for driving two n-channel mosfets in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each driver is capable of driving a 3 nf load at speeds up to 500 khz. a more detailed description of the adp3418 and its features follows. refer to figure 1. low-side driver the low-side driver is designed to drive a ground-referenced n-channel mosfet. the bias to the low-side driver is internally connected to the vcc supply and pgnd. when the driver is enabled, the drivers output is 180 degrees out of phase with the pwm input. when the adp3418 is dis- abled, the low-side gate is held low. high-side driver the high-side driver is designed to drive a floating n-channel mosfet. the bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the bst and sw pins. the bootstrap circuit comprises a diode, d1, and bootstrap capacitor, c bst1 . c bst2 and r bst are included to reduce the high- side gate drive voltage and limit the switch node slew-rate (referred to as a boot-snap? circuit, see the application information section for more details). when the adp3418 is starting up, the sw pin is at ground, so the bootstrap capacitor will charge up to vcc through d1. when the pwm input goes high, the high-side driver will begin to turn on the high-side mosfet, q1, by pulling charge out of c bst1 and c bst2 . as q1 turns on, the sw pin will rise up to v in , forcing the bst pin to v in + v c(bst) , which is enough gate-to-source voltage to hold q1 on. to complete the cycle, q1 is switched off by pulling the gate down to the voltage at the sw pin. when the low-side mosfet, q2, turns on, the sw pin is pulled to ground. this allows the bootstrap capacitor to charge up to vcc again. the high-side drivers output is in phase with the pwm input. when the driver is disabled, the high-side gate is held low. overlap protection circuit the overlap protection circuit prevents both of the main power switches, q1 and q2, from being on at the same time. this is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. the overlap protection circuit accomplishes this by adaptively controlling the delay from the q1 turn off to the q2 turn on, and by internally setting the delay from the q2 turn off to the q1 turn on. to prevent the overlap of the gate drives during the q1 turn off and the q2 turn on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 will begin to turn off (after propagation delay). before q2 can turn on, the overlap protection circuit makes sure that sw has first gone high and then waits for the voltage at the sw pin to fall from v in to 1 v. once the voltage on the sw pin has fallen to 1 v, q2 begins turn on. if the sw pin had not gone high first, then the q2 turn on is delayed by a fixed 120 ns. by waiting for the voltage on the sw pin to reach 1 v or for the fixed delay time, the overlap protection circuit ensures that q1 is off before q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. if sw does not go below 1 v after 240 ns, drvl will turn on. this can occur if the current flowing in the output inductor is negative and is flowing through the high-side mosfet body diode. to prevent the overlap of the gate drives during the q2 turn off and the q1 turn on, the overlap circuit provides an internal delay that is set to 40 ns. when the pwm input signal goes high, q2 will begin to turn off (after a propagation delay), but before q1 can turn on, the overlap protection circuit waits for the voltage at drvl to drop to approximately one sixth of v cc . once the voltage at drvl has reached this point, the overlap protection circuit will wait for the 40 ns internal delay time. once the delay period has expired, q1 will begin turn on.
adp3418 rev. b | page 10 of 16 application information supply c a pacitor sel e ction f o r th e s u p p l y in p u t ( v c c ) o f th e ad p3418, a l o cal b y p a s s ca p a c i to r is r e commende d to r e d u ce t h e n o is e and to su p p ly s o me o f t h e p e a k c u r r en ts dra w n. u s e a 4.7 f , lo w es r ca p a c i t o r . m u l t ila y er cera mic chi p (ml c c) ca p a ci t o rs p r o v ide t h e b e s t com b ina t io n o f lo w esr a nd smal l si ze. k e ep t h e cera mic c a p a ci to r as c l os e as p o s s i b le t o th e adp3418. bootstrap circuit the b o o t s t r a p c i r c ui t us es a charg e s t o r a g e c a p a ci t o r (c bs t ) a n d a dio d e , as sh o w n in f i gur e 1. th es e com p onen ts can b e s e le c t e d a f t e r t h e hig h -side mo s f et has b e en ch os en. th e bo o t s t ra p ca p a ci t o r m u s t ha v e a v o l t a g e ra t i n g t h a t is ab le t o ha nd le t w ic e t h e max i m u m su pply vol t a g e. a m i nim u m 50 v ra t i n g is r e comm e n de d . the c a p a ci t o r val u es ar e det e r m i n e d usin g t h e fol l o w in g e q ua t i on s: gate gate bst2 bst1 v q c c = + 10 ( 1 ) d gate bst2 bst1 bst1 v vcc v c c c ? = + ( 2 ) w h er e q ga t e i s th e t o tal ga t e c h a r g e o f th e h i gh-si d e m o s f et a t v ga te , v ga te is t h e desir e d ga t e dr i v e v o l t a g e (u s u al l y in t h e ra n g e o f 5-10 v , 7 v bein g typ i ca l), a n d v d is t h e v o l t a g e dr o p acr o ss d1. re a r ra n g in g e q u a t i on s 1 an d 2 t o s o lve fo r c bs t1 yi e l d s d gate bst1 v vcc q c ? = 10 c bs t2 ca n t h e n b e fo un d b y r e a r r a n g in g e q ua t i on 1: 1 10 bst gate gate bst2 c v q c ? = f o r e x am pl e, an n t d 6 0 n 0 2 h a s a tot a l g a te ch arge of ab out 12 nc a t v ga te = 7 v . u s in g v c c = 12 v a nd v d = 1 v , w e f i nd c bs t1 = 12 nf a nd c bs t2 = 6.8 nf . g o o d q u ali t y c e ra mic ca p a c i t o rs sh o u ld b e us ed . r bs t i s used f o r s l ew- r a t e li mi tin g t o m i ni m i z e th e ri n g in g a t th e swi t ch n o d e . i t also p r o v i d es pe ak curr en t li m i t i n g th r o ugh d1. an r bs t val u e o f 1.5 ? t o 2.2 ? is a g o o d ch o i ce . the r e sis t o r n e e d s t o b e a b le t o ha ndle a t leas t 250 mw d u e t o th e p e ak curr e n t s th a t f l o w th r o ugh i t . a smal l-sig n al dio d e can b e us e d fo r th e bo o t stra p dio d e d u e to t h e am ple ga t e dr i v e v o l t a g e s u p p lie d b y v cc . t h e b o o t s t r a p dio d e m u st h a ve a mi ni m u m 1 5 v r a t i n g to w i t h st and t h e m a x i m u m supp ly volt age. t h e a v e r age for w ard c u r r e n t c a n b e es t i ma t e d b y max gate avg f f q i = ) ( ( 3 ) w h er e f ma x is t h e max i m u m s w i t chin g f r e q ue n c y o f t h e co n t r o l l er . th e p e ak s u rg e c u r r en t ra t i n g sh o u l d b e calc u l a t e d usin g: bst d peak f r v vcc i ? = ) ( ( 4 ) mosfet selection w h en in t e r f aci n g t h e ad p341 8 t o ext e r n al m o s f et s, t h er e ar e a fe w con s idera t io n s t h a t t h e de sig n er sh o u ld b e a w a r e o f . th e s e wi l l h e l p to ma k e a m o r e r o b u st desig n t h a t wi l l mini mi ze s t r e s s es o n b o t h t h e dr i v er and mos f et s. th e s e s t r e s s es in cl ude exce e d in g t h e sh o r t-t i m e d u ra t i on v o l t a g e ra t i n g s on t h e dr i v er pin s as w e l l as t h e ex t e r n al mos f et . i t is als o hig h l y r e co mmen d e d to us e th e b o o t -s na p cir c ui t t o im p r o v e t h e in terac t io n o f t h e dr i v er wi t h t h e cha r ac t e r i s t ics of th e mos f et s. i f a sim p le bo o t stra p a r ra n g eme n t is us e d , mak e su re to t h e n i n clu d e a prop e r s n ub b e r ne t w or k on t h e s w no d e . high-side (control) mosfe t s the hig h -side mos f et is us ual l y s e le c t e d t o b e hig h sp e e d to minimi ze s w i t chin g los s es (s e e a n y ad i flex-mo d e? co n t r o l l er da ta sh ee t f o r m o r e d e ta ils o n m o s f et los s e s ). t h i s us uall y im plies a lo w ga t e r e sist an ce and lo w in p u t c a p a ci t a n c e/cha r ge de vice . y e t, t h ere is a l s o a sig n if ica n t s o ur ce le a d i n d u c t an ce t h a t ca n exis t (t his dep e n d s ma inl y o n t h e mos f et p a cka g e; i t is b e st t o co n t ac t t h e mos f et v e n d o r fo r t h is info r m a t io n). the ad p3418 d r vh o u t p u t im p e dance and th e in p u t r e sis t a n c e o f th e mos f et s det e r m in e t h e r a t e of c h a r g e del i ve r y to t h e g a te s i n te r n a l c a p a c i t a nc e, w h i c h de te r m i n e s t h e sp e e d a t w h i c h t h e mos f et s t u r n o n an d o f f. h o w e ver , d u e to p o t e n t ia l l y la rge c u r r en ts f l o w in g in t h e mos f et s a t t h e o n an d o f f t i m e s (t his c u r r en t is us ual l y la rg er a t t u r n of f d u e t o r a m p i n g up of t h e output c u r r e n t i n t h e output i n d u c t or ) , t h e s o ur ce le ad i n d u c t a n c e w i l l ge nera t e a sig n if ican t vol t a g e acr o ss i t w h en t h e hig h -side m o s f et s swi t ch o f f . this wil l cr ea t e a sig n if ica n t dra i n-s o ur ce v o l t a g e s p i k e acr o s s t h e in ter n al die o f t h e mos f et s and can le ad to c a t a st r o phic a v a l a n ch e. t h e m e ch a n ism s i n volv e d in t h is a v a l an ch e con d i t ion can b e re f e re nc e d i n l i t e r a tu re f r om t h e m o sf e t sup p l i e r s .
adp3418 rev. b | page 11 of 16 the mos f et ven do r sh o u ld p r o v ide a maxim u m v o l t a g e s l e w r a te a t dr ain c u r r en t r a t i n g such t h a t t h is c a n b e desig n e d a r o u n d . o n c e yo u ha v e t h is sp e c if ica t ion, t h e next st ep is t o det e r m i n e t h e maxim u m c u r r en t yo u exp e c t to s e e in t h e mos f et . this ca n b e don e wi t h t h e fol l o w in g e q u a t i o n : () out max max out dc max l f d v vcc phase per i i ? + = ) ( (5) he r e , d max is de t e r m ine d fo r t h e vr co n t r o l l er bein g us ed wi th t h e dr i v er . ple a s e n o te t h is c u r r en t gets divide d ro ug h l y e q ua l l y betw een m o s f et s if m o r e than on e is us ed (as s u m e a w o rst- cas e misma t c h o f 30% fo r desig n ma rg in). l ou t is t h e o u t p ut ind u c t o r va l u e . w h en p r o d ucing yo ur desig n , th er e is n o exac t m e t h o d fo r calc u l a t i n g t h e dv/ d t d u e t o t h e p a rasi t i c ef fe c t s in t h e ext e r n al m o s f et s as w e l l as th e p c b . h o w e v e r , i t can b e m e as ur ed t o det e r m in e if i t is s a f e . i f i t a p p e a r s th e dv/d t is t o o fas t , an o p t i o n a l ga te r e sisto r ca n b e ad de d b e tw e e n dr vh and t h e hig h -side m o s f et s. this r e sis t o r wil l s l o w do wn the dv /d t, b u t i t w i ll al so in c r ea se t h e swi t c h in g l o s s e s i n t h e hi gh - s i d e m o s f et s. the ad p3418 has b e en o p timal l y desig n e d wi t h a n in ter n a l dr i v e i m p e dance t h a t wi l l w o r k wi t h m o st mos f et s to sw i t ch t h em ef f i cien t l y yet mini mi ze dv/ d t. h o w e v e r , s o m e hig h - s p e e d mo s f et s ma y r e q u ir e t h is ext e r n a l ga t e r e sist o r dep e n d in g on t h e c u r r en ts b e i n g s w i t che d i n t h e mos f e t . low-side (synchrono us) mosfets the lo w-side mos f et s a r e us u a l l y s e le c t e d t o ha v e a lo w on- r e sis t a n c e t o minimize co nd uc t i o n los s es. this us ual l y im p l ies a la rg e in pu t ga t e ca p a c i t a n c e an d ga t e cha r g e . the f i rs t co n c er n is t o mak e s u r e the p o w e r de li v e r y f r o m th e ad p 3418 s d r vl do es n o t exce e d t h e t h er mal ra t i n g o f t h e dr i v er (s e e t h e flex- m o de co n t r o ller da ta sh eet f o r deta ils). the n e xt con c er n fo r t h e lo w-si de mos f et s is b a s e d o n p r ev e n t i n g t h em f r o m i n ad v e r t e n tl y b e i n g swi t c h ed o n w h en t h e hig h -side mos f et t u r n s on. this o c c u rs d u e t o t h e dra i n- ga t e (mi l ler , a l s o sp e c if ie d as c rss ) ca p a ci t a n c e of t h e mos f et . w h en t h e dra i n o f t h e lo w-side mos f et is sw i t che d t o v c c b y t h e hig h -side t u r n in g o n (a t a ra t e dv / d t), t h e in t e r n al ga t e o f th e lo w-side mos f et wil l b e p u l l ed u p b y a n a m o u n t r o ug hl y eq ual t o v c c (c rs s /c iss ). i t is im p o r t a n t t o ma k e s u r e this do es n o t pu t t h e mo s f et in t o cond uc t i o n . an o t h e r co n s id era t io n is t h e n o n-o v erla p c i r c ui t r y o f t h e ad p3418 which a t t e m p ts t o mini mize the n o n-o v erla p p e r i o d . d u r i n g t h e st a t e o f t h e hig h -side t u r n in g o f f t o lo w-side t u r n ing o n , t h e s w pin i s m o n i to r e d (as w e l l as t h e cond i t io n s o f sw pr i o r to s w i t c h i n g ) to a d e q u a tel y pre v e n t ove r l a p . h o w e ver , d u r i ng t h e lo w-side tur n o f f to hig h -side t u r n on, t h e sw p i n do es n o t co n t ain info r m a t ion fo r dete r m inin g t h e p r o p er sw i t ching t i me , s o t h e s t a t e o f t h e d r vl p i n is m o n i to r e d to go b e lo w on e six t h o f v c c and t h e n a d e l a y is adde d . bu t d u e t o t h e mi l l er ca p a ci t a n c e and i n t e r n al dela ys of t h e lo w-side mos f et ga te , o n e m u s t ens u r e t h e mi l l er t o in pu t ca p a c i t a n c e r a t i o is lo w en o u g h a nd t h e lo w-side mos f et i n t e rn al de la ys a r e n o t la r g e en o u gh t o allo w a cci d e n t al t u rn o n o f t h e lo w-side w h en t h e hig h -side t u r n s on. a s p r e adsh e e t is a v a i la b l e f r o m ad i tha t wil l assis t th e desig n er in t h e p r o p er s e le c t io n o f lo w-side mos f et s.
adp3418 rev. b | page 12 of 16 pc board layout considerations u s e t h e fol l o w in g genera l guid e l i n es w h e n des i g n in g p r i n t e d cir c ui t bo a r ds. ? t r ace o u t t h e hi g h c u r r en t p a t h s a nd us e sh o r t, wide (>20 mi l) t r aces t o mak e t h es e c o nn e c t i o n s. ? c o nn ec t the pg nd p i n o f the ad p3418 as c l os e l y as p o s s i b le t o t h e s o ur ce o f th e lo w e r m o s f et . ? the v cc b y pa s s c a pa ci t o r s h o u l d be l o ca t e d a s c l ose a s p o s s i b le t o t h e v c c an d pg nd p i n s . ? u s e vias t o o t h e r la yers when p o s s i b le t o maximize t h er mal c o n d u c t i on a w ay f r om t h e ic . the cir c ui t in f i gur e 15 s h o w s ho w f o ur dr i v ers ca n be co m b in e d wi t h th e ad p3188 t o f o r m a t o tal p o w e r co n v ersio n so l u tio n f o r g e n e ra tin g v cc ( c o r e ) fo r an i n tel cp u t h a t is vrd 10.x co m p lian t. f i gur e 14 s h o w s a n exa m ple o f t h e typ i ca l land p a t t er n s b a s e d o n t h e guide l in e s g i v e n p r e v io usly . f o r m o r e det a i l e d l a yo u t g u i d el i n e s for a c o m p l e te c p u volt age re g u l a tor sub s y s te m, r e f e r t o th e adp3188 da ta sh eet. d1 c bst2 c bst1 r bst c vcc 03229-b - 014 f i gure 14. e x ter n a l compon ent p l ac e m ent e x amp l e for the a d p 3 41 8 d r iver
adp3418 rev. b | page 13 of 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d5 1n 4148 c1 9 4.7 f q13 n t d 60n 02 q15 n t d 110n 02 q16 n t d 110n 02 c1 6 6.8nf c1 7 4.7 f u5 adp 3418 bst 1 in 2 3 vcc 4 drvh sw pg nd drvl 8 7 6 5 l5 320nh/1.4m ? rt h1 100k ? , 5% nt c r6 2.2 ? c2 0 12nf d4 1n 4148 c1 5 4.7 f q9 n t d 60n 02 q11 n t d 110n 02 q12 n t d 110n 02 c1 4 6.8nf c1 3 4.7 f u4 adp 3418 bst 1 in 2 3 vcc 4 drvh sw pg nd drvl 8 7 6 5 l4 320nh/1.4m ? r5 2.2 ? c1 6 12nf d3 1n 4148 c1 1 4.7 f q5 n t d 60n 02 q7 n t d 110n 02 q8 n t d 110n 02 c1 0 6.8nf c9 4.7 f u3 adp 3418 bst 1 in 2 3 vcc 4 drvh sw pg nd drvl 8 7 6 5 d1 1n 4148 l3 320nh/1.4m ? r4 2.2 ? c1 2 12nf d2 1n 4148 c7 4.7 f q1 n t d 60n 02 q3 n t d 110n 02 q4 n t d 110n 02 c6 6.8nf c5 4.7 f u2 adp 3418 bst 1 in 2 3 vcc 4 drvh sw pg nd drvl 8 7 6 5 l4 320nh/1.4m ? r3 2.2 ? c8 12nf + + c24 c 3 1 10 f 1 8 m l cc in socket v cc ( c o r e ) 0.8375 v ? 1.6v 95a td c , 119a p k v cc ( c o r e ) rtn 560 f/4v 8 sanyo sepc seri e s 5m ? each u1 adp 3188 vi d4 vi d3 vi d2 vi d1 vi d0 vi d5 f brt n fb com p pwrg d en del a y rt ram padj vcc pwm 1 pwm 2 pwm 3 pwm 4 sw1 sw2 sw3 sw4 gnd cscom p cssum csref ilimit r ph 1 158k ?, 1% r ph 2 158k ?, 1% r ph 3 158k ?, 1% r ph 4 158k ?, 1% r cs 2 84.5k ? c a 470pf c b 470pf r cs 1 35.7k ? r a 12.1k ? r b 1.21k ? c cs 2 1.5nf c fb 22pf c cs 1 560pf c2 2 1nf r lim 150k ? 1% c2 3 1nf c2 1 1nf po wer good enabl e fr om cpu c ldy 39nf r ldy 470k ? r t 137k ? 1% r2 137k ? 1% + c3 100 f c4 1 f + + c1 c2 li 370nh 18a 2700mf/16v /3.3a 2 sanyo m v - w x seri e s v in 12v v in rt n 0 3229- b - 015 od od od od f i gure 1 5 . vrd 10 .x c o m p li a n t int e l c p u sup p l y c i rcui t
adp3418 rev. b | page 14 of 16 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5 . 00 ( 0 . 1 968) 4 . 80 ( 0 . 1 890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarit y 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa f i g u re 16. 8-l e ad s t anda r d s m a l l o u t l ine p a ckag e [soic ] narro w b o dy (r -8) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s) ordering guide model temperature r a nge package descri ption package option adp3418krz 1 0c to 85c soic rn-8 adp3418krzCreel 1 0c to 85c soic rn-8 1 z = p b -fr ee par t .
adp3418 rev. b | page 15 of 16 notes
adp3418 rev. b | page 16 of 16 notes ? 2004 analo g d e vices, inc. all rights reser v ed. tra d emarks and r e gistered trad e m arks are t h e pr op e r ty o f th eir r e spectiv e o w n e rs. c03229C0 C 8/04(b)

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